module iic_test_top(
    input                                   i_clk                   ,
    output                                  o_i2c_scl               ,
    inout                                   io_i2c_sda              ,
    output                                  o_cep_en                 
);
    assign                              o_cep_en                    = 1'b1;
    wire                                          locked                      ;
    wire                                          rst                       =~locked;
    wire                                          clk_50M                     ;
clk_wiz_0 clk_wiz_0
(
    // Clock out ports
    .clk_out1                           (clk_50M                   ),// output clk_out1
    // Status and control signals
    .locked                             (locked                    ),// output locked
   // Clock in ports
    .clk_in1                            (i_clk                     ) 
);                                                                  // input clk_in1

iic_test iic_test(
    .i_clk                              (clk_50M                   ),
    .i_rst                              (rst                       ),
    .o_i2c_scl                          (o_i2c_scl                 ),
    .io_i2c_sda                         (io_i2c_sda                ) 
);
endmodule
